module Multi_Register_file_REG_A(iClk,iResult,oResult);
  
  input iClk;
  input [7:0] iResult;
  
  output [7:0] oResult;
  
  //reg [7:0] iResult,
  reg [7:0] oResult;
  
  
  always @(posedge iClk)
     begin
          if(1) oResult <= iResult;
      end
  
  
  
endmodule
